IEEE. STD_LOGIC_UNSIGNED. ALL; top modulecycle MIPS TM (J. Hennessy & D. Patterson, 1998). WebPack 9.1i: IF_chip, ID_chip, EX_chip, MEM_chip, CTL_chipA_SPIM is (clock: in std_logic;: in std_logic;: out std_logic_vector (7 downto 0 )); A_SPIM; spim_structure of A_SPIM isID_chip (clock: in std_logic;: in std_logic;: in std_logic_vector (31 downto 0); _data: in std_logic_vector (7 downto 0);: in std_logic;: in std_logic;: out std_logic_vector ( 7 downto 0);: out std_logic_vector (7 downto 0);: out std_logic_vector (7 downto 0);: out std_logic_vector (5 downto 0)); component; IF_chip (clock: in std_logic;: in std_logic; _Address: in std_logic_vector (7 downto 0);: in std_logic;: out std_logic_vector (31 downto 0);: out std_logic_vector (7 downto 0);: out std_logic_vector (7 downto 0)); component; EX_chip (Branch: in std_logic;: in std_logic ;: in std_logic_vector (7 downto 0);: in std_logic_vector (7 downto 0);: in std_logic_vector (7 downto 0);: in std_logic_vector (7 downto 0);: out std_logic_vector (7 downto 0); _Address: out std_logic_vector (7 downto 0);: out std_logic); component; CTL_chip (Op: in std_logic_vector (5 downto 0);: out std_logic;: out std_logic;: out std_logic;: out std_logic;: out std_logic;: out std_logic); component; MEM_chip (clock: in std_logic;: in std_logic;: in std_logic;: in std_logic;: in std_logic_vector (7 downto 0); _data: in std_logic_vector (7 downto 0); _data: out std_logic_vector (7 downto 0)) ; component; NPC_bus: std_logic_vector (7 downto 0); Rs_bus: std_logic_vector (7 downto 0); Rt_bus: std_logic_vector (7 downto 0); OpCode_bus: std_logic_vector (5 downto 0); Imm_bus: std_logic_vector (7 downto 0); BrAddress_bus: std_logic_vector (7 downto 0); ALUresult_bus: std_logic_vector (7 downto 0); write_back_bus: std_logic_vector (7 downto 0); Instruction_bus: std_logic_vector (31 downto 0); Branch_wire: std_logic; PCsrc_wire: std_logic; RegWrite_wire: std_logic; MemtoReg_wire: std_logic; ALUSrc_wire: std_logic; MemWrite_wire: std_logic; RegDst_wire: std_logic; _IF: IF_chip port map (=> clock, => reset, _Address => BrAddress_bus, => PCsrc_wire, => Instruction_bus, => NPC_bus, => PC); _ID: ID_chip port map (=> clock, => reset, => Instruction_bus, _data => write_back_bus, => RegWrite_wire, => RegDst_wire, => Rs_bus, => Rt_bus, => OpCode_bus, => Imm_bus); _EX: EX_chip port map (=> Branch_wire, => ALUSrc_wire, => NPC_bus, => Rs_bus, => Rt_bus, => Imm_bus, => PCsrc_wire, _Address => BrAddress_bus, => ALUResult_bus); _CTL: CTL_chip port map (=> OpCode_bus, => RegDst_wire, => ALUSrc_wire, => MemtoReg_wire, => RegWrite_wire, => MemWrite_wire, => Branch_wire); _MEM: MEM_chip port map (=> clock, => reset, => MemWrite_wire, => MemtoReg_wire, _data => write_back_bus, => ALUResult_bus, _data => Rt_bus); spim_structure;
.2 Модуль Керування (CTL)
Для одноціклової машини Достатньо мати комбінаційній Пристрій Керування. Аджея Кожна машинна інструкція одноразово вібірається з програмної пам'яті, а ее код ПРОТЯГ цього циклу не змінюється.
ctrl_chipIEEE; IEEE. STD_LOGIC_1164. all; IEEE. STD_LOGIC_ARITH. all; ctrl_chip is (: in STD_LOGIC_VECTOR (5 downto 0);: out STD_LOGIC;: out STD_LOGIC;: out STD_LOGIC;: out STD_LOGIC;: out STD_LOGIC;: out STD_LOGIC
); ctrl_chip;
}} End of automatically maintained sectionbehav of ctl_chip isR_for...
