Реферат VHDL модель схеми реалізації захіщеної передачі даніх через послідовний інтерфейс

LOGIC;: out STD_LOGIC); component ; INV_MY (TDELAY: TIME: = 1 ns); (A0: in STD_LOGIC;: out STD_LOGIC); component;

XOR_6 (TDELAY: TIME: = 1 ns); (A0: in STD_LOGIC;: in STD_LOGIC;: in STD_LOGIC;: in STD_LOGIC;: in STD_LOGIC;: in STD_LOGIC;: out STD_LOGIC); component;: XOR_6map ( A0 => NET1957, => NET2641, A2 => NET1930, => NET1922, A4 => Enable, => NET2528, Z0 => NET2976);: INV_MYmap (=> Reset, => ; NET44);: AND2_MYmap (A0 => NET44, => CLK, Z0 => NET1231);

: DFF_MYmap (CLK => NET1231, => NET3011, d1 => Data (0), => Enable, q => NET1957);

: DFF_MYmap (CLK => NET1231, => NET1957, d1 => Data (1), => Enable, q => NET2641);

: DFF_MYmap (CLK => NET1231, => NET2641, d1 => Data (2), => Enable, q => NET1323);

: DFF_MYmap (=> NET1231, Enable => NET1773, d1 => Data (4), d2 => Enable, q => NET1930);

: DFF_MYmap (CLK => NET1231, => NET1930, d1 => Data (5), => Enable, q => NET2677);

: DFF_MYmap (CLK => NET1231, => NET2677, d1 => Data (6), => Enable, q => NET1922);

: DFF_MYmap (CLK => NET1231, => NET1922, d1 => Data (7), => Enable, q => NET1777);

: DFF_MYmap (CLK => NET1231, => NET1777, d1 => Data (8), => Enable, q => NET1590);

: DFF_MYmap (CLK => NET1231, => NET1590, d1 => Data (9), => Enable, q => NET1598);

: DFF_MYmap (CLK => NET1231, => NET1633, d1 => Data (11), d2 => Enable, q => NET1683);

: DFF_MYmap (CLK => NET1231, => NET1683, d1 => Data (12), d2 => Enable, q => NET2528);

: DFF_MYmap (=> NET1231, Enable => NET1323, d1 => Data (3), d2 => Enable, => NET1773);: DFF_MYmap (=> NET1231, Enable => NET1598, d1 => Data (10), d2 => Enable, => NET1633);: BUF_MYmap (=> NET2976, Z1 => NET3011, => Result);

end LFSR_MVD_12;