ерез послідовний інтерфейс В
Додаток 2
Інфоетфейсній описание компоненти "" CU_lfsr_12
library IEEE; IEEE.std_logic_1164.all;
CU_lfsr_12 is (: in STD_LOG IC;: in STD_LOGIC_VECTOR (12 downto 0); _CU: in STD_LOGIC_VECTOR (2 downto 0); _XOR: out STD_LOGIC_VECTOR (1 downto 0);: in STD_LOGIC;: in STD_LOGIC; _lfsr: out STD_LOGIC; _lfsr: out STD_LOGIC_VECTOR (12 downto 0); _lfsr: out STD_LOGIC
); CU_lfsr_12;
Додаток 3
Інтерфейс ний та архітектурний описание компоненти "XOR_cipher
library IEEE; IEEE.std_logic_1164.all; XOR_cipher is (: in STD_LOGIC;: in STD_LOGIC;: in STD_LOGIC;: in STD_LOGIC; _XOR: in STD_LOGIC_VECTOR (1 downto 0);: out STD_LOGIC; : out STD_LOGIC
); XOR_cipher;
XOR_cipher of XOR_cipher is (CLK) a: time; tmp: std_logic;: = 1 ns; CLK = '1 'and CLK'event thenControl_XOR = "00" then: = (In1 XOR In2 ); Result1 <= tmp after a; if; Control_XOR = "01" then: = (In1 XOR In3); Result2 <= tmp after a; if; if; process; XOR_cipher;
Додаток 4
Інтерфейсні та архітектурні опису
компоненти "dff_myIEEE; IEEE.std_logic_1164.all; dff_my is (CLK: in STD_LOGIC; d1: in STD_LOGIC;: in STD_LOGIC; Enable: in STD_LOGIC;: out STD_LOGIC); dff_my; dff_my of dff_my is
-variable data: STD_LOGIC; (Enable, CLK) begin (Enable = '0 ') thenq <= d1; (CLK'event and CLK = '1') thenq <= d2; if; process; end dff_my;
компоненти "XOR_6IEEE; use IEEE.std_logic_1164.all; XOR_6 is (TDELAY: TIME: = 1 ns); (A0: in STD_LOGIC; A1: in STD_LOGIC; A2: in STD_LOGIC;: in STD_LOGIC; A4: in STD_LOGIC ; A5: in STD_LOGIC;: out STD_LOGIC); XOR_6; XOR_6 of XOR_6 is (A0, A1, A2, A3, A4, A5) pZ0: std_logic; variable iZ0: std_logic;: = iZ0;: = (A0 XOR (A1 XOR (A2 XOR (A3 XOR (A4 XOR (A5)))))); pZ0/= iZ0 thenZ0 <= transport iZ0 after TDELAY; <= transport iZ0; if; process; XOR_6;
компоненти "lfsr_mvdIEEE; IEEE.std_logic_1164.all; lfsr_mvd_12 is (CLK: in STD_LOGIC;: in STD_LOGIC;: in STD_LOGIC;: in STD_LOGIC_VECTOR (12 downto 0);: out STD_LOGIC); lfsr_mvd_12; LFSR_MVD_12 of lfsr_mvd_12 isNET1231: STD_LOGIC; NET1323: STD_LOGIC; NET1590: STD_LOGIC; NET1598: STD_LOGIC; NET1633: STD_LOGIC; NET1683: STD_LOGIC; NET1773: STD_LOGIC; NET1777: STD_LOGIC; NET1922: STD_LOGIC; NET1930: STD_LOGIC; NET1957: STD_LOGIC; NET2528: STD_LOGIC; NET2641: STD_LOGIC; NET2677: STD_LOGIC; NET2976: STD_LOGIC; NET3011: STD_LOGIC; NET44: STD_LOGIC; AND2_MY (: TIME: = 1 ns
); (A0: in STD_LOGIC;: in STD_LOGIC;: out STD_LOGIC
); component; BUF_MY (A: in STD_LOGIC;: out STD_LOGIC;: out STD_LOGIC); component; DFF_MY (CLK: in STD_LOGIC;: in STD_LOGIC;: in STD_LOGIC;: in STD_...
