/p>
------------------------------------------ ------------- fir_filtr is
(data_size: INTEGER: = 18; _size: INTEGER: = 20; _size: INTEGER: = 8; _count: INTEGER: = 4; fir: INTEGER: = 2
);
(clk: in std_logic;: in std_logic;: in std_logic;: in std_logic_vector (data_size - 1 downto 0); _sum: out std_logic_vector (data_size - 1 downto 0)
); fir_filtr; Behavioral of fir_filtr ismem_unit is
(data_size: INTEGER: = 18; _size: INTEGER: = 20; _size: INTEGER: = 8; _count: INTEGER: = 4
); (clk: in std_logic; - загальні сигнали для модуля: in std_logic;: in std_logic;: in std_logic_vector (data_size - 1 downto 0); _rom: in std_logic_vector (adr_size - 1 downto 0);: in std_logic_vector (adr_size - 1 downto 0);: in std_logic_vector (adr_size - 1 downto 0); _rom: in std_logic;: in std_logic; _rom: out std_logic_vector (coef_size - 1 downto 0);: inout std_logic_vector ( data_size - 1 downto 0);: inout std_logic_vector (data_size - 1 downto 0)
); component; CU is (_size: INTEGER: = 8; _count: INTEGER: = 4
);
(: IN STD_LOGIC;: IN STD_LOGIC;: IN STD_LOGIC;: OUT STD_LOGIC;: OUT STD_LOGIC; _out: OUT STD_LOGIC; _sum: OUT STD_LOGIC; _A: INOUT STD_LOGIC_VECTOR (adr_size - 1 DOWNTO 0) ; _B: OUT STD_LOGIC_VECTOR (adr_size - 1 DOWNTO 0)
); component; SignedMul18x20 is (
data_size: INTEGER: = 18; - розрядність вхідних данних_size: INTEGER: = 20 - розрядність коефіцієнтів
);
port (: in std_logic;: in std_logic_vector (data_size - 1 downto 0);: in std_logic_vector (coef_size - 1 downto 0); _A: out std_logic_vector (data_size + coef_size - 1 downto 0)
); component; f_sum is (_size: INTEGER: = 18; _size: INTEGER: = 20;
log2fir: INTEGER: = 2); - збільшення розрядної сітки
- з урахуванням кол-ва
- коефіцієнтів в ПЗУ (: in std_logic;: in std_logic;: in std_logic; _sum_A: in std_logic_vector (data_size + coef_size - 1 downto 0); _sum: out std_logic_vector (data_size - 1 downto 0 )
); component; Iram_A: std_logic_vector (data_size - 1 downto 0); Icoef: std_logic_vector (coef_size - 1 downto 0); Iadr_A, Iadr_B: std_logic_vector (adr_size - 1 downto 0); Ien_cu, Irst_sum , Ird1, Iwr1: std_logic; Imul_A: std_logic_vector (data_size + coef_size - 1 downto 0);
begin: mem_unit - отримання даних з пам'яті
generic map (18, 20, 8, 4)
port map (clk => clk, en => Ien_cu, rst => rst, adc => adc, adr_rom => Iadr_A, adrA => Iadr_A, adrB => ; Iadr_B, rd_rom => Ird1, wr1 => Iwr1, do_rom => Icoef, doA => Iram_A, doB => open); _I: cu - отримання сигналів з блоку CU <...
