data
data (0)
1
0
X
0.data
data (1)
VHDL КОД
library IEEE;
use IEEE.std_logic_1164.all;
entity regpiso is port (
);
end entity;
CLK: in std_logic; LOAD: in std_logic;
DATA: in std_logic_vector (31 downto 0); SO: out std_logic
architecture regpiso of regpiso is
signal TEMP_SO: std_logic_vector (31 downto 0);
begin
process (CLK)
begin
if rising_edge (CLK) then if LOAD = '1 'then
TEMP_SO <= DATA;
end if;
end process;
else end if;
TEMP_SO <= '0 '& TEMP_SO (31 downto 1);
SO <= TEMP_SO (0);
end architecture;
Блок пристрої керування
Пристрій управління реалізувати керуючим а автоматом граф переходів, якого описати в редакторі FSM
read
ask
c
num
load
clk1
clk2
stb
ready
0
X
X
0
0
0
0
0
1
X
0
x
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
X
X
1
1
0
0
1
1
0
x
x
1
2
0
1
0
0
0
....
...
..
...
...
.....
...
...
....
x
x
1
32
0
0
1
1
0
X
X
1
0
0
1
0
0
1
VHDL Код
library IEEE;
use IEEE.std_logic_1164.all;
entity FUNC is port (
ASK: in STD_LOGIC; LOAD: in STD_LOGIC; READ: in STD_LOGIC; WR: in STD_LOGIC;
ADDR: in STD_LOGIC_VECTOR (7 downto 0); KEY: in STD_LOGIC_VECTOR (29 downto 0); N: in STD_LOGIC_VECTOR (3 downto 0);
X: in STD_LOGIC_VECTOR (31 downto 0); READY: out STD_LOGIC;
READYO: out STD_LOGIC; RESULT: out STD_LOGIC; STB : Out STD_LOGIC
);
end FUNC;
architecture FUNC of FUNC is
---- Component declarations ----- component bcode
port (
CLK: in STD_LOGIC;
DATA: in STD_LOGIC_VECTOR (29 downto 0); DIN: in STD_LOGIC;
LOAD: in STD_LOGIC; SO: out STD_LOGIC
);
end component; component f port (
N: in STD_LOGIC_VECTOR (3 downto 0); X: in STD_LOGIC_VECTOR (31 downto 0); Y: out STD_LOGIC_VECTOR (31 downto 0)
);
end component; component kontroler port (
ASK: in STD_LOGIC; C: in STD_LOGI...
