ts AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- PROGRAM Quartus II
- VERSION Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
- CREATED Tue May 20 15:35:09 2014 ieee; ieee.std_logic_1164.all; work; rzu IS
(: IN STD_LOGIC ;: IN STD_LOGIC; _AI: IN STD_LOGIC; _BI: IN STD_LOGIC; _AO: IN STD_LOGIC; _BO: IN STD_LOGIC; _AI: IN STD_LOGIC_VECTOR (4 DOWNTO 0); _ AO: IN STD_LOGIC_VECTOR (4 DOWNTO 0); _ BI: IN STD_LOGIC_VECTOR (4 DOWNTO 0); _ BO: IN STD_LOGIC_VECTOR (4 DOWNTO 0) ;: IN STD_LOGIC_VECTOR (7 DOWNTO 0) ;: IN STD_LOGIC_VECTOR (7 DOWNTO 0) ;: IN STD_LOGIC_VECTOR (8 DOWNTO 6) ;: IN STD_LOGIC_VECTOR (1 DOWNTO 0) ;: IN STD_LOGIC_VECTOR (2 DOWNTO 0) ;: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ;: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
); rzu; bdf_type OF rzu IS ronparam (nR: INTEGER
); (WR_AI: IN STD_LOGIC; _BI: IN STD_LOGIC; _AO: IN STD_LOGIC; _BO: IN STD_LOGIC ;: IN STD_LOGIC ;: IN STD_LOGIC; _AI: IN STD_LOGIC_VECTOR (4 DOWNTO 0); _ AO:IN STD_LOGIC_VECTOR (4 DOWNTO 0); _ BI: IN STD_LOGIC_VECTOR (4 DOWNTO 0); _ BO: IN STD_LOGIC_VECTOR (4 DOWNTO 0) ;: IN STD_LOGIC_VECTOR (7 DOWNTO 0) ;: IN STD_LOGIC_VECTOR (7 DOWNTO 0) ;: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ;: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
); COMPONENT; shift_out (DI: IN STD_LOGIC_VECTOR (7 DOWNTO 0) ;: IN STD_LOGIC_VECTOR (8 DOWNTO 6) ;: IN STD_LOGIC_VECTOR (1 DOWNTO 0) ;: IN STD_LOGIC_VECTOR (2 DOWNTO 0) ;: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
); COMPONENT; shift_out_a (DI: IN STD_LOGIC_VECTOR (7 DOWNTO 0) ;: IN STD_LOGIC_VECTOR (8 DOWNTO 6) ;: IN STD_LOGIC_VECTOR (1 DOWNTO 0) ;: IN STD_LOGIC_VECTOR (2 DOWNTO 0) ;: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
); COMPONENT ;: STD_LOGIC_VECTOR (7 DOWNTO 0) ;: STD_LOGIC_VECTOR (7 DOWNTO 0); v_inst: ronparamMAP (nR= gt; 7
) MAP (WR_AI= gt; WR_AI, _BI= gt; WR_BI, _AO= gt; EN_AO, _BO= gt; EN_BO,= gt; CLK,= gt; RST, _AI= gt; ADR_AI , _AO= gt; ADR_AO, _BI= gt; ADR_BI, _BO= gt; ADR_BO,= gt; AI,= gt; BI,= gt; Aout,= gt; Bout); v_inst1: shift_outMAP (DI= gt; Bout, = gt; I,= gt; M,= gt; N,= gt; BO); v_inst2: shift_out_aMAP (DI= gt; Aout,= gt; I,= gt; M,= gt; N,= gt; AO ); bdf_type;
Висновок
У ході виконання даної лабораторної роботи, я із застосуванням VHDL і методики налагодження в САПР Quartus II зумів побудувати параметричний блок РОН, вхідний і вихідний сдвігатель. Потім зібрав РЗУ використовуючи написані бібліотеки (РОН, сдвігатель).
