on (31 downto 26); _addr1 <= Instruction (25 downto 21); _addr2 <= Instruction (20 downto 16); _addr_ALUop < =Instruction (15 downto 11); _addr_LWop <= Instruction (20 downto 16); <= Instruction (7 downto 0); rd_addr1 (4 downto 0) select <= x «00» when «00000», when «00001», when «00010», when «00011», when «00100», when «00101», when «00110», when «00111», « FF » when others; rd_addr2 (4 downto 0) select <= x «00» when «00000», when «00001», when «00010», when «00011», when «00100», when «00101», when «00110», when «00111», « FF » when others; _addr <= wr_addr_ALUop when RegDst=«1» else wr_addr_LWop; wr <= «1» when ((wr_addr=«00001») and (RegWrite=«1»)) else «0»; wr <= «1» when ((wr_addr=«00010») and (RegWrite=«1»)) else «0»; wr <= «1» when ((wr_addr=«00011») and (RegWrite=«1»)) else «0»; wr <= «1» when ((wr_addr=«00100») and (RegWrite=«1»)) else «0»; wr <= «1» when ((wr_addr=«00101») and (RegWrite=«1»)) else «0»; wr <= «1» when ((wr_addr=«00110») and (RegWrite=«1»)) else «0»; wr <= «1» when ((wr_addr=«00111») and (RegWrite=«1»)) else «0»; tmp <= write_data when reg1wr=«1» else reg1; tmp <= write_data when reg2wr=«1» else reg2; tmp <= write_data when reg3wr=«1» else reg3; tmp <= write_data when reg4wr=«1» else reg4; tmp <= write_data when reg5wr=«1» else reg5; tmp <= write_data when reg6wr=«1» else reg6; tmp <= write_data when reg7wr=«1» else reg7; until clock «event and clock =» 1 «; reset =» 1 'then <= x «A1»; <= x «A2»; <= x «A3»; <= x « A4 »; <= x« A5 »; <= x« A6 »; <= x« A7 »; <= reg1tmp; <= reg2tmp; <= reg3tmp; <= reg4tmp; <= reg5tmp; <= reg6tmp; <= reg7tmp; if; process; behav;
.4 Mодуль IF
IF chipIEEE; IEEE. STD_LOGIC_1164. ALL; IEEE. STD_LOGIC_ARITH. ALL; IEEE. STD_LOGIC_UNSIGNED. ALL; IF_chip is (clock: in std_logic;: in std_logic;: in std_logic; _Address: in std_logic_vector (7 downto 0);: out std_logic_vector (7 downto 0);: out std_logic_vector (31 downto 0);: out std_logic_vector ( 7 downto 0)); IF_chip; behav of IF_chip isPC: std_logic_vector (7 downto 0); Input_PC: std_logic_vector (7 downto 0); NPC_temp: std_logic_vector (7 downto 0); Programrom0: std_logic_vector (31 downto 0):=x « 8c040000 »; $ 4, 0 ($ 0) rom1: std_logic_vector (31 downto 0):=x« 8c050001 »; $ 5, 1 ($ 0) rom2: std_logic_vector (31 downto 0):=x« 00852020 »; $ 4, $ 4, $ 5 rom3: std_logic_vector (31 downto 0):=x «ac040000»; $ 4, 0 ($ 0) rom4: std_logic_vector (31 downto 0):=x «1080fffb»; $ 4, $ 0, - 20rom5: std_logic_vector (31 downto 0): =x «1084ffff»; $ 4, $ 4, - 4rom6: std_logic_vector (31 downto 0):=x «00000025»; $ 0, $ 0, $ 0rom7: std_logic_vector (31 downto 0):=x «00000025»; $ 0, $ 0, $ 0 <= PC; _temp (7 downto 2) <= PC (7 downto 2) + 1; _temp (1 downto 0) <= b «00»; <= NPC_temp; _PC <= Branch_Address when PCsrc =«1» else NPC_temp; until (clock «event) and (clock =» 1 «); reset =» 1 'then <= x «00»; <= Input_PC; if; process; (PC) PC (7 downto 2 ) is «000000» => instruction <= rom0; «000001» => instruction <= rom1; «000010» => instruction <= rom2; «000011» => instruction <= rom3; «000100» => instruction <= rom4; «000101» => instruction <= rom5; «000110» => instruction <= rom6; «000111» => instruction <= rom7; others => instruction <= x «00000000»; case; process; behav;
.5 Модуль пам яті (МЕМ)
Призначе...
