W_SIZE_CD +1 +6); _Im_3 (X_Y_WIDTH + W_SIZE_CD +1 +7) <= addIm3_out (X_Y_WIDTH + W_SIZE_CD +1 + 6); _Re_4 (X_Y_WIDTH + W_SIZE_CD +1 +7) <= addRe4_out (X_Y_WIDTH + W_SIZE_CD +1 +6); _Im_4 (X_Y_WIDTH + W_SIZE_CD +1 +7) <= addIm4_out (X_Y_WIDTH + W_SIZE_CD +1 +6) ;
-_Re_1 (X_Y_WIDTH + W_SIZE_CD +1 +8) <= addRe1_out (X_Y_WIDTH + W_SIZE_CD +1 +6); _Im_1 (X_Y_WIDTH + W_SIZE_CD +1 +8) <= addIm1_out (X_Y_WIDTH + W_SIZE_CD +1 +6); _Re_2 (X_Y_WIDTH + W_SIZE_CD +1 +8) <= addRe2_out (X_Y_WIDTH + W_SIZE_CD +1 +6); _Im_2 (X_Y_WIDTH + W_SIZE_CD +1 +8) <= addIm2_out (X_Y_WIDTH + W_SIZE_CD + 1 +6); _Re_3 (X_Y_WIDTH + W_SIZE_CD +1 +8) <= addRe3_out (X_Y_WIDTH + W_SIZE_CD +1 +6); _Im_3 (X_Y_WIDTH + W_SIZE_CD +1 +8) <= addIm3_out (X_Y_WIDTH + W_SIZE_CD +1 + 6); _Re_4 (X_Y_WIDTH + W_SIZE_CD +1 +8) <= addRe4_out (X_Y_WIDTH + W_SIZE_CD +1 +6); _Im_4 (X_Y_WIDTH + W_SIZE_CD +1 +8) <= addIm4_out (X_Y_WIDTH + W_SIZE_CD +1 +6) ; IF; IF; RISING_EDGE (clk_160) THEN - accum (Clk_160) THEN - accum - Shift C_D; process; (CLK_160) - counter ZRISING_EDGE (CLK_160) THENRES_160 = '1 'THEN_Z <= 0; (COUNT_H1 = 1) THEN_Z <= COUNT_Z + 1; _Z <= COUNT_Z; IF; IF ; process; (CLK_160) - counter hRISING_EDGE (CLK_160) THEN_160 <= NRD AND MS (1) AND not CORR_ENA; _160D <= RES_160; _M160 <= (NOT RES_160D) AND RES_160; IF; _H <= COUNT_H1P; RISING_EDGE (CLK_160) THEN_H4 <= COUNT_H + ((3 * corr_depth)/4); _H3 <= COUNT_H + ((2 * corr_depth)/4); _H2 <= COUNT_H + (corr_depth/4); _H1 <= COUNT_H + 0; RES_160 = '1 'THEN_H1P <= 0; (CORR_ENA = '1' and mult_ENA = '1 ') THEN_H1P <= COUNT_H1P + 1; IF; IF; RISING_EDGE (CLK_160) THENMS_M160 ( 1) = '1 'THEN <= 0; (CORR_ENA = '1') THEN <= timer + 1; IF; IF; process; (CLK_160) - out enablingRISING_EDGE (CLK_160) THENtimer = 0 THEN_o <= '1 '; timer = (corr_depth/4) THEN_o <= '0'; en_o <= en_o; IF; IF; process; _en <= en_o; Behavioral;
Додаток Б - програмний код модуля В«mem_drvВ»
IEEE; IEEE.STD_LOGIC_1164.ALL; IEEE.NUMERIC_STD.ALL; IEEE.STD_LOGIC_SIGNED.ALL; mem_drv is
(corr_depth: natural: = 256; _SIZE_CD: natural: = 6
); (in_C: IN STD_LOGIC_VECTOR (W_SIZE_CD-1 downto 0); _D: IN STD_LOGIC_VECTOR (W_SIZE_CD-1 downto 0); _ENA: IN STD_LOGIC; _ROM: OUT INTEGER RANGE 0 to 255; _RAM1 : OUT INTEGER RANGE 0 to 127; _RAM2: OUT INTEGER RANGE 0 to 127; _RAM3: OUT INTEGER RANGE 0 to 127; _RAM4: OUT INTEGER RANGE 0 to 127; _RAM_1: OUT STD_LOGIC;: IN STD_LOGIC_VECTOR (2 * W_SIZE_CD-1 downto 0);: IN STD_LOGIC_VECTOR (2 * W_SIZE_CD-1 downto 0);: IN STD_LOGIC_VECTOR (2 * W_SIZE_CD-1 downto 0);: IN STD_LOGIC_VECTOR (2 * W_SIZE_CD-1 downto 0); _160: IN STD_LOGIC;: OUT STD_LOGIC_VECTOR (2 * W_SIZE_CD-1 downto 0);: OUT STD_LOGIC_VECTOR (2 * W_SIZE_CD-1 downto 0);: OUT STD_LOGIC_VECTOR (2 * W_SIZE_CD-1 downto 0);: OUT STD_LOGIC_VECTOR (2 * W_SIZE_CD-1 downto 0); _RAM1 : IN INTEGER RA...
