NGE 0 to 63; _RAM_2: OUT STD_LOGIC; _IN: OUT STD_LOGIC_VECTOR (2 * W_SIZE_CD-1 downto 0)
); mem_drv; Behavioral of mem_drv isIWE_RAM_1: STD_LOGIC; IWE_RAM_2: STD_LOGIC; NCORR: STD_LOGIC; RWR: STD_LOGIC; DRWR: STD_LOGIC; DDRWR: STD_LOGIC; RW_EN: STD_LOGIC; DNCORR: STD_LOGIC; DDNCORR: STD_LOGIC ; CORR: STD_LOGIC; COUNT: INTEGER RANGE 0 TO corr_depth; DCOUNT: INTEGER RANGE 0 TO corr_depth; DDCOUNT: INTEGER RANGE 0 TO (corr_depth/2) -1; <= not CORR_ENA; _IN (W_SIZE_CD-1 downto 0) < ; = in_C; _IN (2 * W_SIZE_CD-1 downto W_SIZE_CD) <= in_D; (DDRWR) DDRWR is'0 '=> ADRR_RAM1 <= AD_RAM1; _RAM2 <= AD_RAM1 +64; _RAM3 <= AD_RAM1; _RAM4 <= AD_RAM1 +64;
------------------ <= INCD1; <= INCD2; <= INCD3; <= INCD4; '1 '= > ADRR_RAM1 <= DDCOUNT; _RAM2 <= 0; _RAM3 <= DDCOUNT; _RAM4 <= 0;
------------------ <= "000000000000"; <= "000000000000"; <= "000000000000"; <= "000000000000"; others => _RAM1 <= 0; _RAM2 <= 0; _RAM3 <= 0; _RAM4 <= 0;
------------------ <= "000000000000"; <= "000000000000"; <= "000000000000"; <= "000000000000"; case; process; (RWR) RWR is'0 '=> ADRR_ROM <= 0; '1' => ADRR_ROM <= COUNT; others => ADRR_ROM <= 0 ; case; process;
- CD1 <= INCD1;
- CD2 <= INCD2;
- CD3 <= INCD3;
- CD4 <= INCD4; (CLK_160) beginRISING_EDGE (CLK_160) THEN_RAM_1 <= IWE_RAM_1; _RAM_2 <= IWE_RAM_2; <= RWR; <= DRWR; IF; _EN <= RWR or DRWR or DDRWR; RISING_EDGE (CLK_160) THENDCOUNT <127 and RWR = '1 'THEN_RAM_1 <= '1'; _RAM_2 <= '0 ';> = 127 and RWR =' 1'_RAM_1 <= '0 '; _RAM_2 <= '1'; _RAM_1 <= '0 '; _RAM_2 <= '0'; IF; <= COUNT; <= DCOUNT; <= NCORR ; <= DNCORR; <= (NOT DDNCORR) AND DNCORR; IF; process;
- (CLK_160) beginRISING_EDGE (CLK_160) THENCORR = '1 'THEN <= '1'; = 255 <= '0 '; RWR <= RWR; IF; IF; process; (CLK_160 ) - counterRISING_EDGE (CLK_160) THENCORR = '1 'THEN <= 0; (RWR = '1') THEN <= COUNT + 1; <= COUNT; IF; IF; process; Behavioral;
