enSendInfo=«0» and num_bit=0InfoOut <= «0»; if; start_read=true thennum_bit=11InfoOut <= «1»; _bit:=0; _bit:=true; if; num_bit=13 <= (adress (3) xor adress (2) xor adress (1) xor adress (0) data (0) xor data (1) xor data (2) xor data (3) xor data (4)); _bit:=14; if; num_bit= 12InfoOut <= data (6); _bit:=13; if; num_bit=11 InfoOut <= data (5); _bit:=12; if; num_bit=10InfoOut <= data (4); _bit:=11 ; if; num_bit=9InfoOut <= data (3); _bit:=10; if; num_bit=8InfoOut <= data (2); _bit:=9; if; num_bit=7InfoOut <= data (1); _bit:=8; if; num_bit=6InfoOut <= data (0); _bit:=7; if; num_bit=5InfoOut <= adress (0); _bit:=6; if; num_bit=4InfoOut <= adress (1); _bit:=5; if; num_bit=3InfoOut <= adress (2); _bit:=4; if; num_bit=2InfoOut <= adress (3); _bit:=3; if; num_bit=1InfoOut <= «1»; _bit:=2; if; if; SendInfo=«1» and num_bit=0if last_bit=truelast_bit:=false; _read:=true; _bit:=1; (0):=O1; (1):=O2, (2):=O3; (3):=O4; ( 4):=Pereezd; (6 downto 5):=FStatus; if; if; if; if; process; mine;
Додаток Б
Лістинг програми ПЛІС БМП
-
- Title: mine
- Design: work
- Author: Alexey Kuprienko
- Company: Home
- File: ІЬУ.vhd
- Generated: Sun Dec 4 17:21:15 2005
- From: interface description file
- By: Itf2Vhdl ver. 1.20
-
- Description: курсовий проект по МИУС Купрієнко Олексія -
- Description:
- Design unit header - IEEE; IEEE.std_logic_1164.all; BME is (R1: in STD_LOGIC; R2: in STD_LOGIC; R1: in STD_LOGIC; R2: in STD_LOGIC; R1: in STD_LOGIC; R2: in STD_LOGIC;: out STD_LOGIC;: out STD_LOGIC;: out STD_LOGIC;: out STD_LOGIC;: out STD_LOGIC;: out STD_LOGIC
); BME; BME of BME is
--- Component declarations ----- FE (: in STD_LOGIC;: in STD_LOGIC;: out STD_LOGIC;: out STD_LOGIC
); component; spt (: in STD_LOGIC;: in STD_LOGIC;: in STD_LOGIC;: in STD_LOGIC;: out STD_LOGIC;: out STD_LOGIC
); component;
--- Signal declarations used on the diagram ---- NET122: STD_LOGIC; NET126: STD_LOGIC; NET130: STD_LOGIC; NET134: STD_LOGIC; NET138: STD_LOGIC; NET142: STD_LOGIC; NET295: STD_LOGIC; NET299 : STD_LOGIC; NET303: STD_LOGIC; NET307: STD_LOGIC; NET317: STD_LOGIC; NET321: STD_LOGIC;
--- Component instantiations ----: sptmap (=> K2R1, => K2R2, => NET138, => NET142, => NET303, => NET307
);: FEmap (=> NET303, => NET307, => SSVR21, => SSVR22
);: FEmap (=> NET295, => NET299, => SSVR11, => SSVR12
);: FEmap (=> NET317, => NET321, => SSVR31, => SSVR32
);: sptmap (=> K1R1, => K1R2, => NET122, => NET126, => NET295, => NET299
);: sptmap (=> K3R1, => K3R2, => NET130, => NET134, => NET317, => NET321
); <= not (K3R2); <= not (K3R1); <= not (K2R2); <= not (K2R1); <= not (K1R2); <= not (K1R1); BME;
- Title: Фіксуючий елемент
- Design: First
- Author: 123
- Company: 456
