ons used on the diagram ---- NET107: STD_LOGIC; NET115: STD_LOGIC; NET91: STD_LOGIC; NET99: STD_LOGIC;
--- Component instantiations ---- <= In2 or In1; <= In4 or In3; <= In2 and In1; <= In4 and In3; <= NET99 and NET91; <= NET115 or NET107; spt;
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- Title: парафазного тригер
- Design: First
- Author: 123
- Company: 456
-
- Description:
- Design unit header - IEEE; IEEE.std_logic_1164.all; pt is (: in STD_LOGIC;: in STD_LOGIC;: in STD_LOGIC;: in STD_LOGIC;: out STD_LOGIC;: out STD_LOGIC
); pt; pt of pt is
--- Signal declarations used on the diagram ---- NET102: STD_LOGIC; NET204: STD_LOGIC; NET230: STD_LOGIC; NET232: STD_LOGIC; NET236: STD_LOGIC; NET239: STD_LOGIC; NET240: STD_LOGIC; NET340 : STD_LOGIC; NET343: STD_LOGIC; NET344: STD_LOGIC; NET444: STD_LOGIC; NET447: STD_LOGIC; NET448: STD_LOGIC; NET556: STD_LOGIC; NET568: STD_LOGIC; NET580: STD_LOGIC; NET592: STD_LOGIC; NET67: STD_LOGIC; NET71: STD_LOGIC; NET88: STD_LOGIC ;
--- Component instantiations ---- <= not (NET102 and Reset and T0); <= not (NET236); <= not (NET240); <= not ( NET239); <= not (NET230); <= NET232 or NET240; <= not (NET344 and Set and T1); <= not (NET568 and Reset and NET340); <= not (NET340); <= not (NET343); <= not (NET556 and Set and NET204); <= not (NET448 and Reset and T1); <= not (NET592 and Set and NET444); <= not (NET444 ); <= not (NET447); <= not (NET204); <= not (NET102); <= not (NET88); <= not (NET67); <= NET71 or NET102; < ;=not (NET240 and Set and T0); <= not (NET580 and Reset and NET236); pt;
- Title: парафазного генератор
- Design: First
- Author: 123
- Company: 456
- Description:
- Design unit header - IEEE; IEEE.std_logic_1164.all; PTGen is (: out STD_LOGIC;: out STD_LOGIC); PTGen; STRUCTURA of PTGen isCLK_PERIOD: TIME:=10 us; _GEN: Process <= «0»; <= «1»; for CLK_PERIOD / 2; <= «1»; <= «0»; for CLK_PERIOD / 2; process; STRUCTURA;
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- Title: Формувач сигналу відновлення Пт2
- Design: First
- Author: 123
- Company: 456
- Description:
- Design unit header - IEEE; IEEE.std_logic_1164.all; Vosstan is (: out STD_LOGIC); Vosstan; STRUCTURA of PTGen is_GEN: processi: bit:=«0»; i=« ; 0 » thenfor 7us;:=«1»; if; <= «1»; for 0.3us; <= «0»; for 82us; process;
end STRUCTURA;
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- Title: Формувач сигналу початкового скидання ПТ1
- Design: First
- Author: 123
- Company: 456
- Description:
- Design unit header - IEEE; IEEE.std_logic_1164.all; sbros is (...
