ектор Довжина 4 біта, Який утворюється в результаті Перетворення в S-блоці.
2.1 Розроблення структурного Опису прилаштую
Код бібліотеки:
library ieee; ieee.std_logic_1164.all; my_func isS1 (in1: in STD_LOGIC_VECTOR (0 to 5); out1: out STD_LOGIC_VECTOR (0 to 3)); component; S2 (in2: in STD_LOGIC_VECTOR (0 to 5); out2: out STD_LOGIC_VECTOR (0 to 3)); component; S3 (in3: in STD_LOGIC_VECTOR (0 to 5); out3: out STD_LOGIC_VECTOR (0 to 3)); component; S4 (in4: in STD_LOGIC_VECTOR (0 to 5); out4: out STD_LOGIC_VECTOR (0 to 3)); component; S5 (in5: in STD_LOGIC_VECTOR (0 to 5); out5: out STD_LOGIC_VECTOR (0 to 3)); component; S6 (in6: in STD_LOGIC_VECTOR (0 to 5); out6: out STD_LOGIC_VECTOR (0 to 3)); component; S7 (in7: in STD_LOGIC_VECTOR (0 to 5); out7: out STD_LOGIC_VECTOR (0 to 3)); component; S8 (in8: in STD_LOGIC_VECTOR (0 to 5); out8: out STD_LOGIC_VECTOR (0 to 3)); component; package my_func;
-Тіло пакету.body my_func ispackage body my_func; ieee; ieee.std_logic_1164.all; S1 is (in1: in STD_LOGIC_VECTOR (0 to 5); out1: out STD_LOGIC_VECTOR (0 to 3)); S1; model_S1 of S1 isin1 select (0) <= '1 'when
'0 'when others; in1 select (1) <= '1' when
'0 'when others; in1 select (2) <= '1' when
'0 'when others; in1 select (3) <= '1' when
'0 'when others; model_S1; ieee; ieee.std_logic_1164.all; S2 is (in2: in STD_LOGIC_VECTOR (0 to 5); out2: out STD_LOGIC_VECTOR (0 to 3)); S2; model_S2 of S2 isin2 select (0) <= '1 'when
'0 'when others; in2 select (1) <= '1' when
'0 'when others; in2 select (2) <= '1' when
'0 'when others; in2 select (3) <= '1' when
'0 'when others; model_S2; ieee; ieee.std_logic_1164.all; S3 is (in3: in STD_LOGIC_VECTOR (0 to 5); out3: out STD_LOGIC_VECTOR (0 to 3)); S3; model_S3 of S3 isin3 select (0) <= '1 'when
'0 'when others; in3 select (1) <= '1' when
'0 'when others; in3 select (2) <= '1' when
'0 'when others; in3 select (3) <= '1' when
'0 'when others; model_S3; ieee; ieee.std_logic_1164.all; S4 is (in4: in STD_LOGIC_VECTOR (0 to 5); out4: out STD_LOGIC_VECTOR (0 to 3)); S4; model_S4 of S4 isin4 select (0) <= '1 'when
'0 'when others; in4 select (1) <= '1' when
'0 'when others; in4 select (2) <= '1' when
'0 'when others; in4 select (3) <= '1' when
'0 'when others; model_S4; ieee; ieee.std_logic_1164.all; S5 is (in5: in STD_LOGIC_VECTOR (0 to 5); out5: out STD_LOGIC_VECTOR (0 to 3)); S5; model_S5 of S5 isin5 select (0) <= '1 'when
'0 'when others; in5 select (1) <= '1' when
'0 'when others; in5 select (2) <= &...
