ce.vhd
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
-library UNISIM;
-use UNISIM.VComponents.all;
sorce is (
A: in std_logic_vector (3 downto 0);, rst, clk: in std_logic;: out std_logic_vector (7 downto 0)
В
); sorce;
Behavioral of sorce ismult4x4_u is (
A : in std_logic_vector (3 downto 0); : in std_logic_vector (3 downto 0); : out std_logic_vector (7 downto 0)
); component;
reg1: std_logic_vector (3 downto 0); sA, sB: std_logic_vector (3 downto 0); sP, sAA: std_logic_vector (7 downto 0); s: std_logic;
: mult4x4_u port map (A, reg1, sP);
(clk, rst)
begin
if rst = '1 'then
reg1 <= "0000";
elsif clk = '1 'and clk'event then
if load = '1 'then
reg1 <= A;
end if;
end if;
end process;
: process (clk) clk = '1 'and clk'event then <= sP; if; process ; Behavioral;
mult4x4_u.vhd
IEEE; IEEE.std_logic_1164.all;
-
- pragma translate_offUNISIM; UNISIM.VCOMPONENTS.ALL;
- pragma translate_on
-mult4x4_u is (
A: in std_logic_vector (3 downto 0); : in std_logic_vector (3 downto 0); : out std_logic_vector (7 downto 0)
); mult4x4_u;
-mult4x4_u_arch of mult4x4_u is
-
- Components Declarations:
- MULT18X18 (
A: in std_logic_vector (17 downto 0);
B: in std_logic_vector (17 downto 0);
P: out std_logic_vector (35 downto 0)
); component;
-
A_int: std_logic_vector (17 downto 0); B_int: std_logic_vector (17 downto 0); P_int: std_logic_vector (35 downto 0);
_int (17 downto 8) <= "0000000000"; _int (7 downto 4) <= "0000"; _int (3 downto 0) <= A (3 downto 0 ); _int (17 downto 4) <= "00000000000000"; _int (3 downto 0) <= B (3 downto 0);
